diff options
| author | Santosh Shilimkar | 2012-07-04 17:57:34 +0530 |
|---|---|---|
| committer | Benoit Cousson | 2012-09-07 19:18:41 +0200 |
| commit | 926fd45ba9eeb4c3d0454b934161ee884dd82a22 (patch) | |
| tree | cc72dae1f1078300d513e4f6dd76d094c8ba22d9 /arch/arm/boot | |
| parent | 11c27069cf963f7445a7b515bcb703d90ae0c162 (diff) | |
ARM: OMAP4: Add L2 Cache Controller in Device Tree
Provide PL310 Level 2 Cache Controller Device Tree
support for OMAP4 based devices.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/dts/omap4.dtsi | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index c7dc11feb9da..cb18d2a2971c 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -30,12 +30,21 @@ cpus { cpu@0 { compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; }; cpu@1 { compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; }; }; + L2: l2-cache-controller@48242000 { + compatible = "arm,pl310-cache"; + reg = <0x48242000 0x1000>; + cache-unified; + cache-level = <2>; + }; + /* * The soc node represents the soc top level view. It is uses for IPs * that are not memory mapped in the MPU view or for the MPU itself. |