diff options
| author | Nicolas Pitre | 2011-05-03 15:30:34 -0400 |
|---|---|---|
| committer | Nicolas Pitre | 2011-05-03 15:39:05 -0400 |
| commit | f5178ddd2f09de8b1cfc5e19043892e8b24666cb (patch) | |
| tree | 1df301d8bf3b57a2c95a7b77270188909cce3a36 /arch/arm/boot | |
| parent | 0ffd3c4805446dc00a042140443fd7342a35d0b4 (diff) | |
ARM: PJ4: remove the ARMv6 compatible cache method entries
The Marvell PJ4 is ARMv7 capable, so we don't support it in
ARMv6 mode anymore.
Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
Acked-by: Saeed Bishara <saeed.bishara@gmail.com>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/compressed/head.S | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index adf583cd0c35..a36f4526689b 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -735,12 +735,6 @@ proc_types: W(b) __armv4_mmu_cache_off W(b) __armv6_mmu_cache_flush - .word 0x560f5810 @ Marvell PJ4 ARMv6 - .word 0xff0ffff0 - W(b) __armv4_mmu_cache_on - W(b) __armv4_mmu_cache_off - W(b) __armv6_mmu_cache_flush - .word 0x000f0000 @ new CPU Id .word 0x000f0000 W(b) __armv7_mmu_cache_on |