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| author | Nicolas Pitre | 2008-09-11 15:14:59 -0400 |
|---|---|---|
| committer | Nicolas Pitre | 2008-09-30 13:41:54 -0400 |
| commit | 99c6bb390cf599b9e0aa6e69beacc4e5d875bf77 (patch) | |
| tree | d30e32867cd161001e5ae6fecc51a52f469bbaff /arch/arm/configs/orion5x_defconfig | |
| parent | 92a5de80e5c53c56d098ea3cb6266138efd892f6 (diff) | |
[ARM] Feroceon: small cleanups to L2 cache code
- Make sure that coprocessor instructions for range ops are contiguous
and not reordered.
- s/invalidate_and_disable_dcache/flush_and_disable_dcache/
- Don't re-enable I/D caches if they were not enabled initially.
- Change some masks to shifts for better generated code.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Acked-by: Lennert Buytenhek <buytenh@marvell.com>
Diffstat (limited to 'arch/arm/configs/orion5x_defconfig')
0 files changed, 0 insertions, 0 deletions