diff options
| author | Lennert Buytenhek | 2009-11-24 19:33:52 +0200 |
|---|---|---|
| committer | Nicolas Pitre | 2009-11-27 15:43:21 -0500 |
| commit | 573a652fb0da50a1ff3fca2c67afd81138fd06d2 (patch) | |
| tree | e393e667f733db56447c266d45e58accf141894f /arch/arm/include | |
| parent | edabd38e1a017e922e3e3b485ee3ddb4df433aa4 (diff) | |
ARM: Add Tauros2 L2 cache controller support
Support for the Tauros2 L2 cache controller as used with the PJ1
and PJ4 CPUs.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/hardware/cache-tauros2.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/include/asm/hardware/cache-tauros2.h b/arch/arm/include/asm/hardware/cache-tauros2.h new file mode 100644 index 000000000000..538f17ca905b --- /dev/null +++ b/arch/arm/include/asm/hardware/cache-tauros2.h @@ -0,0 +1,11 @@ +/* + * arch/arm/include/asm/hardware/cache-tauros2.h + * + * Copyright (C) 2008 Marvell Semiconductor + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +extern void __init tauros2_init(void); |