diff options
| author | Arnd Bergmann | 2019-09-02 17:47:55 +0200 |
|---|---|---|
| committer | Krzysztof Kozlowski | 2020-08-20 21:00:15 +0200 |
| commit | 71b9114d2c13a648fbe6523dd859e611c316ad90 (patch) | |
| tree | c380a723099f776736779319be913f8c0900989e /arch/arm/mach-s3c/sleep-s3c2410.S | |
| parent | a3814e55b411e8cdb352637c65925f60b9ac15cc (diff) | |
ARM: s3c: move into a common directory
s3c24xx and s3c64xx have a lot in common, but are split across three
separate directories, which makes the interaction of the header files
more complicated than necessary.
Move all three directories into a new mach-s3c, with a minimal
set of changes to each file.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
[krzk: Rebase, add s3c24xx and s3c64xx suffix to several files, add SPDX
headers to new files, remove plat-samsung from MAINTAINERS]
Co-developed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
https://lore.kernel.org/r/20200806182059.2431-39-krzk@kernel.org
Diffstat (limited to 'arch/arm/mach-s3c/sleep-s3c2410.S')
| -rw-r--r-- | arch/arm/mach-s3c/sleep-s3c2410.S | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c/sleep-s3c2410.S b/arch/arm/mach-s3c/sleep-s3c2410.S new file mode 100644 index 000000000000..0340297596e9 --- /dev/null +++ b/arch/arm/mach-s3c/sleep-s3c2410.S @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2004 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * S3C2410 Power Manager (Suspend-To-RAM) support + * + * Based on PXA/SA1100 sleep code by: + * Nicolas Pitre, (c) 2002 Monta Vista Software Inc + * Cliff Brake, (c) 2001 + */ + +#include <linux/linkage.h> +#include <linux/serial_s3c.h> +#include <asm/assembler.h> +#include <mach/map.h> + +#include <mach/regs-gpio.h> +#include <mach/regs-clock.h> + +#include "regs-mem-s3c24xx.h" + + /* s3c2410_cpu_suspend + * + * put the cpu into sleep mode + */ + +ENTRY(s3c2410_cpu_suspend) + @@ prepare cpu to sleep + + ldr r4, =S3C2410_REFRESH + ldr r5, =S3C24XX_MISCCR + ldr r6, =S3C2410_CLKCON + ldr r7, [r4] @ get REFRESH (and ensure in TLB) + ldr r8, [r5] @ get MISCCR (and ensure in TLB) + ldr r9, [r6] @ get CLKCON (and ensure in TLB) + + orr r7, r7, #S3C2410_REFRESH_SELF @ SDRAM sleep command + orr r8, r8, #S3C2410_MISCCR_SDSLEEP @ SDRAM power-down signals + orr r9, r9, #S3C2410_CLKCON_POWER @ power down command + + teq pc, #0 @ first as a trial-run to load cache + bl s3c2410_do_sleep + teq r0, r0 @ now do it for real + b s3c2410_do_sleep @ + + @@ align next bit of code to cache line + .align 5 +s3c2410_do_sleep: + streq r7, [r4] @ SDRAM sleep command + streq r8, [r5] @ SDRAM power-down config + streq r9, [r6] @ CPU sleep +1: beq 1b + ret lr |