diff options
| author | Ard Biesheuvel | 2021-02-11 09:19:46 +0100 |
|---|---|---|
| committer | Russell King | 2021-03-09 10:25:17 +0000 |
| commit | c0e50736e826b51ddc437e6cf0dc68f07e4ad16b (patch) | |
| tree | 06b10b3e8e4f25d4792eb8e6e1ded3c1297fd6fa /arch/arm/mm/cache-v7.S | |
| parent | c4e792d1acce31c2eb7b9193ab06ab94de05bf42 (diff) | |
ARM: 9057/1: cache-v7: add missing ISB after cache level selection
A write to CSSELR needs to complete before its results can be observed
via CCSIDR. So add a ISB to ensure that this is the case.
Acked-by: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'arch/arm/mm/cache-v7.S')
| -rw-r--r-- | arch/arm/mm/cache-v7.S | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index dc8f152f3556..307f381eee71 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -38,9 +38,10 @@ icache_size: * procedures. */ ENTRY(v7_invalidate_l1) - mov r0, #0 - mcr p15, 2, r0, c0, c0, 0 - mrc p15, 1, r0, c0, c0, 0 + mov r0, #0 + mcr p15, 2, r0, c0, c0, 0 @ select L1 data cache in CSSELR + isb + mrc p15, 1, r0, c0, c0, 0 @ read cache geometry from CCSIDR movw r1, #0x7fff and r2, r1, r0, lsr #13 |