diff options
| author | Catalin Marinas | 2005-06-30 17:04:14 +0100 |
|---|---|---|
| committer | Russell King | 2005-06-30 17:04:14 +0100 |
| commit | abaf48a05a8f097654e746af2a5afb2ab95861a1 (patch) | |
| tree | 80cd0d34086e3cb8c1781e317b49c84ad6c97841 /arch/arm/mm | |
| parent | c28a814f25d48f193565003223df0ae617796892 (diff) | |
[PATCH] ARM: 2779/1: Fix the V bit setting for the ARM1020x CPUs
Patch from Catalin Marinas
This patch fixes the V bit setting for the ARM1020x processors. At
reset, this bit is automatically set to the value of the HIVECSINIT
input signal which just happened to be 1 but it is not mandatory.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm')
| -rw-r--r-- | arch/arm/mm/proc-arm1020.S | 4 | ||||
| -rw-r--r-- | arch/arm/mm/proc-arm1020e.S | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S index e69f1940ab39..5c0ae5260d1c 100644 --- a/arch/arm/mm/proc-arm1020.S +++ b/arch/arm/mm/proc-arm1020.S @@ -445,14 +445,14 @@ __arm1020_setup: /* * R * .RVI ZFRS BLDP WCAM - * .0.1 1001 ..11 0101 FIXME: why no V bit? + * .011 1001 ..11 0101 */ .type arm1020_cr1_clear, #object .type arm1020_cr1_set, #object arm1020_cr1_clear: .word 0x593f arm1020_cr1_set: - .word 0x1935 + .word 0x3935 __INITDATA diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S index 142a2c2d6f0b..d69389c4d4ba 100644 --- a/arch/arm/mm/proc-arm1020e.S +++ b/arch/arm/mm/proc-arm1020e.S @@ -427,14 +427,14 @@ __arm1020e_setup: /* * R * .RVI ZFRS BLDP WCAM - * .0.1 1001 ..11 0101 /* FIXME: why no V bit? */ + * .011 1001 ..11 0101 */ .type arm1020e_cr1_clear, #object .type arm1020e_cr1_set, #object arm1020e_cr1_clear: .word 0x5f3f arm1020e_cr1_set: - .word 0x1935 + .word 0x3935 __INITDATA |