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authorArnd Bergmann2017-11-07 16:23:57 +0100
committerArnd Bergmann2017-11-07 16:23:57 +0100
commit1e11cbf720c294c6d574b6f57a4f2a8ba99a441c (patch)
treee4606f0a94c768b8432e8770d0f33b2ab5324b00 /arch/arm64/boot
parent87f89ace81d0978a1049a92c6a9921de5aa0a9e3 (diff)
parent6f8c539313d884f4715b328e1ce4a3987649b97e (diff)
Merge tag 'v4.15-rockchip-dts64-2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt
Pull "Rockchip dts64 updates for 4.15 part2" from Heiko Stübner: Support for the RGA (raster graphics accelerator) on rk3399 and efuses on rk3368. * tag 'v4.15-rockchip-dts64-2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: dts: rockchip: add efuse for RK3368 SoCs arm64: dts: rockchip: add RGA device node for RK3399 clk: rockchip: add more rk3188 graphics clock ids clk: rockchip: add clock id for PCLK_EFUSE256 of RK3368 SoCs
Diffstat (limited to 'arch/arm64/boot')
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3368.dtsi16
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399.dtsi11
2 files changed, 27 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 19fbaa5e7bdd..ead1b47b66ae 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -786,6 +786,22 @@
status = "disabled";
};
+ efuse256: efuse@ffb00000 {
+ compatible = "rockchip,rk3368-efuse";
+ reg = <0x0 0xffb00000 0x0 0x20>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&cru PCLK_EFUSE256>;
+ clock-names = "pclk_efuse";
+
+ cpu_leakage: cpu-leakage@17 {
+ reg = <0x17 0x1>;
+ };
+ temp_adjust: temp-adjust@1f {
+ reg = <0x1f 0x1>;
+ };
+ };
+
gic: interrupt-controller@ffb71000 {
compatible = "arm,gic-400";
interrupt-controller;
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index a65f7f744a40..d340b58ab184 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1204,6 +1204,17 @@
status = "disabled";
};
+ rga: rga@ff680000 {
+ compatible = "rockchip,rk3399-rga";
+ reg = <0x0 0xff680000 0x0 0x10000>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
+ clock-names = "aclk", "hclk", "sclk";
+ resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
+ reset-names = "core", "axi", "ahb";
+ power-domains = <&power RK3399_PD_RGA>;
+ };
+
efuse0: efuse@ff690000 {
compatible = "rockchip,rk3399-efuse";
reg = <0x0 0xff690000 0x0 0x80>;