diff options
| author | Yoshihiro Kaneko | 2019-06-24 12:52:24 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven | 2019-07-29 15:36:00 +0200 |
| commit | 3ed1db9071fde0ba9c4ce22a9b404887c0dbe909 (patch) | |
| tree | 93fd18b444f087012ddd17cc71dab249271bf47f /arch/arm64/boot | |
| parent | 4193a39240fbeda2ee35232bd0a1deedd41d31aa (diff) | |
arm64: dts: renesas: r8a77995: Add cpg reset for DU
Add CPG reset properties to DU node of D3 (r8a77995) SoC.
According to Laurent Pinchart, R-Car Gen3 reset is handled at the group
level so specifying one reset entry per group is sufficient.
This patch was inspired by a patch in the BSP by
Takeshi Kihara <takeshi.kihara.df@renesas.com>.
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm64/boot')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a77995.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 0a344eb55094..ca6aeabd6d04 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -1001,6 +1001,8 @@ clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; clock-names = "du.0", "du.1"; + resets = <&cpg 724>; + reset-names = "du.0"; vsps = <&vspd0 0 &vspd1 0>; status = "disabled"; |