diff options
| author | Mark Brown | 2022-07-04 18:03:01 +0100 |
|---|---|---|
| committer | Will Deacon | 2022-07-05 11:45:47 +0100 |
| commit | 2bc589bd645fd085bb7f621a6e2a723a40fd8948 (patch) | |
| tree | 33c73e983d42ce153dae893626c7eb1c605f5867 /arch/arm64/include/asm | |
| parent | 12c897b4ffecce971e6654e952a0f6453976b3bc (diff) | |
arm64/sysreg: Convert ID_AA64SMFR0_EL1 to automatic generation
Convert ID_AA64SMFR0_EL1 to automatic register generation as per DDI0487H.a,
no functional change.
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20220704170302.2609529-28-broonie@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'arch/arm64/include/asm')
| -rw-r--r-- | arch/arm64/include/asm/sysreg.h | 18 |
1 files changed, 0 insertions, 18 deletions
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index ee7ecba7f498..2e2b5811e081 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -193,7 +193,6 @@ #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) #define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4) -#define SYS_ID_AA64SMFR0_EL1 sys_reg(3, 0, 0, 4, 5) #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0) #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1) @@ -760,23 +759,6 @@ #define ID_AA64ZFR0_EL1_AES_PMULL128 0x2 #define ID_AA64ZFR0_EL1_SVEver_SVE2 0x1 -/* id_aa64smfr0 */ -#define ID_AA64SMFR0_EL1_FA64_SHIFT 63 -#define ID_AA64SMFR0_EL1_I16I64_SHIFT 52 -#define ID_AA64SMFR0_EL1_F64F64_SHIFT 48 -#define ID_AA64SMFR0_EL1_I8I32_SHIFT 36 -#define ID_AA64SMFR0_EL1_F16F32_SHIFT 35 -#define ID_AA64SMFR0_EL1_B16F32_SHIFT 34 -#define ID_AA64SMFR0_EL1_F32F32_SHIFT 32 - -#define ID_AA64SMFR0_EL1_FA64_IMP 0x1 -#define ID_AA64SMFR0_EL1_I16I64_IMP 0xf -#define ID_AA64SMFR0_EL1_F64F64_IMP 0x1 -#define ID_AA64SMFR0_EL1_I8I32_IMP 0xf -#define ID_AA64SMFR0_EL1_F16F32_IMP 0x1 -#define ID_AA64SMFR0_EL1_B16F32_IMP 0x1 -#define ID_AA64SMFR0_EL1_F32F32_IMP 0x1 - /* id_aa64mmfr0 */ #define ID_AA64MMFR0_ECV_SHIFT 60 #define ID_AA64MMFR0_FGT_SHIFT 56 |