diff options
| author | Will Deacon | 2021-02-12 15:09:34 +0000 |
|---|---|---|
| committer | Will Deacon | 2021-02-12 15:09:34 +0000 |
| commit | c974a8e574f9644aba0607958a3abce596699dc1 (patch) | |
| tree | 22db764b922cbd83fa8497099fb162581a6b99da /arch/arm64/include | |
| parent | 1d32854ea76331d10d376ed3ac67831b94466ae9 (diff) | |
| parent | 8ee37e0f97ec66b953d202257293670efaab1daa (diff) | |
Merge branch 'for-next/perf' into for-next/core
Perf and PMU updates including support for Cortex-A78 and the v8.3 SPE
extensions.
* for-next/perf:
drivers/perf: Replace spin_lock_irqsave to spin_lock
dt-bindings: arm: add Cortex-A78 binding
arm64: perf: add support for Cortex-A78
arm64: perf: Constify static attribute_group structs
drivers/perf: Prevent forced unbinding of ARM_DMC620_PMU drivers
perf/arm-cmn: Move IRQs when migrating context
perf/arm-cmn: Fix PMU instance naming
perf: Constify static struct attribute_group
perf: hisi: Constify static struct attribute_group
perf/imx_ddr: Constify static struct attribute_group
perf: qcom: Constify static struct attribute_group
drivers/perf: Add support for ARMv8.3-SPE
Diffstat (limited to 'arch/arm64/include')
| -rw-r--r-- | arch/arm64/include/asm/sysreg.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 8b5e7e5c3cc8..767bb2d47be9 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -291,7 +291,11 @@ #define SYS_PMSFCR_EL1_ST_SHIFT 18 #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5) -#define SYS_PMSEVFR_EL1_RES0 0x0000ffff00ff0f55UL +#define SYS_PMSEVFR_EL1_RES0_8_2 \ + (GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\ + BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0)) +#define SYS_PMSEVFR_EL1_RES0_8_3 \ + (SYS_PMSEVFR_EL1_RES0_8_2 & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) #define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0 @@ -844,6 +848,9 @@ #define ID_AA64DFR0_PMUVER_8_5 0x6 #define ID_AA64DFR0_PMUVER_IMP_DEF 0xf +#define ID_AA64DFR0_PMSVER_8_2 0x1 +#define ID_AA64DFR0_PMSVER_8_3 0x2 + #define ID_DFR0_PERFMON_SHIFT 24 #define ID_DFR0_PERFMON_8_1 0x4 |