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author | Murali Karicheri | 2017-07-04 16:23:24 +0530 |
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committer | David S. Miller | 2017-07-05 09:23:53 +0100 |
commit | 371444764b9882d754d1e67dd212c932359a2293 (patch) | |
tree | 481610b7bace6165ba28cfe1c54eeb9151d8133b /arch/arm64 | |
parent | 908a7733250a2ebcacfafb2ebe0f25c853ac7fdc (diff) |
net: phy: dp83867: add workaround for incorrect RX_CTRL pin strap
The data manual for DP83867IR/CR, SNLS484E[1], revised march 2017,
advises that strapping RX_DV/RX_CTRL pin in mode 1 and 2 is not
supported (see note below Table 5 (4-Level Strap Pins)).
There are some boards which have the pin strapped this way and need
software workaround suggested by the data manual. Bit[7] of
Configuration Register 4 (address 0x0031) must be cleared to 0. This
ensures proper operation of the PHY.
Implement driver support for device-tree property meant to advertise
the wrong strapping.
[1] http://www.ti.com/lit/ds/snls484e/snls484e.pdf
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
[nsekhar@ti.com: rebase to mainline, code simplification]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/arm64')
0 files changed, 0 insertions, 0 deletions