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authorAndre Przywara2024-06-25 00:21:10 +0100
committerChen-Yu Tsai2024-07-11 00:43:10 +0800
commit6ed9a85f1c44d7049cf2d488bfe71252ce467dc2 (patch)
tree8b61fe207e7138f8aad338d8fc7fcb240ac511fe /arch/arm64
parent0ce1d34678e5d214746ee4887f9f7714c39e331f (diff)
arm64: dts: allwinner: h616: add crypto engine node
The Allwinner H616 SoC contains a crypto engine very similar to the H6 version, but with all base addresses in the DMA descriptors shifted by two bits. This requires a new compatible string. Also the H616 CE relies on the internal osciallator for the TRNG operation, so we need to reference this clock. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Link: https://lore.kernel.org/r/20240624232110.9817-5-andre.przywara@arm.com [wens@csie.org: fix up register range size] Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Diffstat (limited to 'arch/arm64')
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
index bf4d41ecbfdc..b29ce7321317 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
@@ -150,6 +150,16 @@
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x40000000>;
+ crypto: crypto@1904000 {
+ compatible = "allwinner,sun50i-h616-crypto";
+ reg = <0x01904000 0x800>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>,
+ <&ccu CLK_MBUS_CE>, <&rtc CLK_IOSC>;
+ clock-names = "bus", "mod", "ram", "trng";
+ resets = <&ccu RST_BUS_CE>;
+ };
+
syscon: syscon@3000000 {
compatible = "allwinner,sun50i-h616-system-control";
reg = <0x03000000 0x1000>;