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authorJon Hunter2016-06-29 12:07:33 +0100
committerThierry Reding2016-07-14 16:20:23 +0200
commit9168e1db754383ea16b75ffcc1efbb9b09cfae64 (patch)
tree7250af8df5e4e594fb2c4a9fed640f4f1ba82794 /arch/arm64
parentd23e054c66ec3daa91ef4ea43d9a99ea65d4e8da (diff)
arm64: tegra: Correct Tegra210 XUSB mailbox interrupt
The XUSB mailbox interrupt for Tegra210 is 40 and not 49 which is for the XUSB pad controller. For some Tegra210 boards, this is causing USB connect and disconnect events to go undetected. Fix this by changing the interrupt number for the XUSB mailbox to 40. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm64')
-rw-r--r--arch/arm64/boot/dts/nvidia/tegra210.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index ac1fb886ca4c..b7318804f400 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -629,7 +629,7 @@
reg-names = "hcd", "fpci", "ipfs";
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>,
<&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,