diff options
| author | Vignesh Raghavendra | 2023-03-20 10:19:35 +0530 |
|---|---|---|
| committer | Greg Kroah-Hartman | 2023-05-11 23:03:10 +0900 |
| commit | a9b3ef13ebddbdaabf63f19f8fa01a17165c22fb (patch) | |
| tree | c680c87e2d1cb452fa46181822da96c2d0eb49e2 /arch/arm64 | |
| parent | fe9dc0a2643e6fa1866f8056095a8466381d73dd (diff) | |
arm64: dts: ti: k3-am62a7: Correct L2 cache size to 512KB
[ Upstream commit 438b8dc949bf45979c32553e96086ff1c6e2504e ]
Per AM62Ax SoC datasheet[0] L2 cache is 512KB.
[0] https://www.ti.com/lit/gpn/am62a7 Page 1.
Fixes: 5fc6b1b62639 ("arm64: dts: ti: Introduce AM62A7 family of SoCs")
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20230320044935.2512288-2-vigneshr@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-am62a7.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-am62a7.dtsi b/arch/arm64/boot/dts/ti/k3-am62a7.dtsi index 331d89fda29d..f1ebaec404fb 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a7.dtsi @@ -96,7 +96,7 @@ L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; - cache-size = <0x40000>; + cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; }; |