diff options
| author | Mark Rutland | 2014-08-01 10:23:20 +0100 |
|---|---|---|
| committer | Will Deacon | 2014-08-01 14:00:06 +0100 |
| commit | ea1719672f59eeb85829073b567495c4f472ac9f (patch) | |
| tree | 32d444492c335db8d243243226822bb105ad446f /arch/arm64 | |
| parent | 94156675847c14a9b16e91b035da32e35e98ef79 (diff) | |
arm64: add newline to I-cache policy string
Due to a missing newline in the I-cache policy detection log output,
it's possible to get some ratehr unfortunate output at boot time:
CPU1: Booted secondary processor
Detected VIPT I-cache on CPU1CPU2: Booted secondary processor
Detected VIPT I-cache on CPU2CPU3: Booted secondary processor
Detected VIPT I-cache on CPU3CPU4: Booted secondary processor
Detected PIPT I-cache on CPU4CPU5: Booted secondary processor
Detected PIPT I-cache on CPU5Brought up 6 CPUs
SMP: Total of 6 processors activated.
This patch adds the missing newline to the format string, cleaning up
the output.
Fixes: 59ccc0d41b7a ("arm64: cachetype: report weakest cache policy")
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/kernel/cpuinfo.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index f82f7d1c468e..f798f66634af 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -52,7 +52,7 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) if (l1ip == ICACHE_POLICY_AIVIVT); set_bit(ICACHEF_AIVIVT, &__icache_flags); - pr_info("Detected %s I-cache on CPU%d", icache_policy_str[l1ip], cpu); + pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu); } static int check_reg_mask(char *name, u64 mask, u64 boot, u64 cur, int cpu) |