diff options
| author | Marc Zyngier | 2013-06-11 18:05:25 +0100 |
|---|---|---|
| committer | Marc Zyngier | 2013-08-09 13:19:28 +0100 |
| commit | f142e5eeb724cfbedd203b32b3b542d78dbe2545 (patch) | |
| tree | 59f6c4d3927ecceecb9541d194e4ec9c8a12db0b /arch/arm64 | |
| parent | 1bbd80549810637b7381ab0649ba7c7d62f1342a (diff) | |
arm64: KVM: add missing dsb before invalidating Stage-2 TLBs
When performing a Stage-2 TLB invalidation, it is necessary to
make sure the write to the page tables is observable by all CPUs.
For this purpose, add dsb instructions to __kvm_tlb_flush_vmid_ipa
and __kvm_flush_vm_context before doing the TLB invalidation itself.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/kvm/hyp.S | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm64/kvm/hyp.S b/arch/arm64/kvm/hyp.S index 218802f68b20..1ac0bbbdddb2 100644 --- a/arch/arm64/kvm/hyp.S +++ b/arch/arm64/kvm/hyp.S @@ -604,6 +604,8 @@ END(__kvm_vcpu_run) // void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa); ENTRY(__kvm_tlb_flush_vmid_ipa) + dsb ishst + kern_hyp_va x0 ldr x2, [x0, #KVM_VTTBR] msr vttbr_el2, x2 @@ -625,6 +627,7 @@ ENTRY(__kvm_tlb_flush_vmid_ipa) ENDPROC(__kvm_tlb_flush_vmid_ipa) ENTRY(__kvm_flush_vm_context) + dsb ishst tlbi alle1is ic ialluis dsb sy |