diff options
| author | Alexander Shiyan | 2014-04-26 08:52:10 +0400 |
|---|---|---|
| committer | Shawn Guo | 2014-05-16 23:02:05 +0800 |
| commit | 09e96a896e10d1dc2b48ce13e9f5b26f65690382 (patch) | |
| tree | 527acfd2e6a27d1fa6716c49f2033659f12ead9b /arch/arm | |
| parent | 388130b07e23c19a0f138361c5e0a8fc5df0b199 (diff) | |
ARM: dts: imx27-phytec-phycore-rdk: Add CSI enable switch
This patch adds a GPIO fixed regulator which used on RDK to
enable CSI bus.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts index ac18ccfa9309..72c773e2bf98 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts @@ -38,6 +38,20 @@ }; }; + regulators { + regulator@2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csien>; + reg = <2>; + regulator-name = "CSI_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 24 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + }; + usbphy { usbphy2: usbphy@2 { compatible = "usb-nop-xceiv"; @@ -83,6 +97,12 @@ &iomuxc { imx27_phycore_rdk { + pinctrl_csien: csiengrp { + fsl,pins = < + MX27_PAD_USB_OC_B__GPIO2_24 0x0 + >; + }; + pinctrl_cspi1cs1: cspi1cs1grp { fsl,pins = < MX27_PAD_CSPI1_SS1__GPIO4_27 0x0 |