diff options
| author | Fabio Estevam | 2014-04-16 08:25:56 -0300 |
|---|---|---|
| committer | Shawn Guo | 2014-05-16 23:01:59 +0800 |
| commit | 22869087463b31c73daf32f5570b928403469656 (patch) | |
| tree | c322386a3cbec0c85b03a8aed7ac38934a3e2676 /arch/arm | |
| parent | 2636c1e27fef19e337b8dd7dcc79dd443399fe1a (diff) | |
ARM: dts: imx27-phytec-phycore-som: Move PMIC IRQ GPIO into a separate pin group
The hardware is better described if we place the PMIC IRQ GPIO into its own
pingroup.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi index d7ed63c51c6c..33c5dc2be89b 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi @@ -69,6 +69,8 @@ #address-cells = <1>; #size-cells = <0>; compatible = "fsl,mc13783"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; reg = <0>; spi-cs-high; spi-max-frequency = <20000000>; @@ -204,7 +206,6 @@ MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* SPI1 CS0 */ - MX27_PAD_USB_PWR__GPIO2_23 0x0 /* PMIC IRQ */ >; }; @@ -251,6 +252,12 @@ >; }; + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX27_PAD_USB_PWR__GPIO2_23 0x0 /* PMIC IRQ */ + >; + }; + pinctrl_ssi1: ssi1grp { fsl,pins = < MX27_PAD_SSI1_FS__SSI1_FS 0x0 |