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| author | Thomas Gleixner | 2020-03-29 22:20:48 +0200 |
|---|---|---|
| committer | Thomas Gleixner | 2020-03-29 22:20:48 +0200 |
| commit | 8a13b02a010a743ea0725e9a5454f42cddb65cf0 (patch) | |
| tree | 16e823aa423af872dcaf316ae91da9f99f2b9bb1 /arch/arm | |
| parent | ba947241f125b19bb6f08a78c22827b9f6a1317a (diff) | |
| parent | 771df8cf0bc3a9a94bc16a58da136cad186cea27 (diff) | |
Merge tag 'irqchip-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core
Pull irqchip updates from Marc Zyngier:
- Second batch of the GICv4.1 support saga
- Level triggered interrupt support for the stm32 controller
- Versatile-fpga chained interrupt fixes
- DT support for cascaded VIC interrupt controller
- RPi irqchip initialization fixes
- Multi-instance support for the Xilinx interrupt controller
- Multi-instance support for the PLIC interrupt controller
- CPU hotplug support for the PLIC interrupt controller
- Ingenic X1000 TCU support
- Small fixes all over the shop (GICv3, GICv4, Xilinx, Atmel, sa1111)
- Cleanups (setup_irq removal, zero-length array removal)
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/common/sa1111.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c index 947ef7981d92..c98ebae1aeac 100644 --- a/arch/arm/common/sa1111.c +++ b/arch/arm/common/sa1111.c @@ -302,10 +302,13 @@ static int sa1111_retrigger_irq(struct irq_data *d) break; } - if (i == 8) + if (i == 8) { pr_err("Danger Will Robinson: failed to re-trigger IRQ%d\n", d->irq); - return i == 8 ? -1 : 0; + return 0; + } + + return 1; } static int sa1111_type_irq(struct irq_data *d, unsigned int flags) |