diff options
| author | Enrik Berkhan | 2009-03-05 14:42:30 +0800 |
|---|---|---|
| committer | Bryan Wu | 2009-03-05 14:42:30 +0800 |
| commit | 7acab7a9ca6b0c5b820f083424c57e6ac2031d9d (patch) | |
| tree | 87e26cbb5c6bbea695679d7bf3953a07817bc39c /arch/blackfin | |
| parent | c18e99cfba746ab0ad8d45e1f351ed990947c58c (diff) | |
Blackfin arch: fix bug - The SPORT_HYS bit is not set for BF561 0.5
IMHO the setting should depend on ANOMALY_05000305 which is about the
availability of the bit, not ANOMALY_05000265 which only describes the
SPORT sensitivity to noise (checked for BF561 only, though).
If that's not true for other BF variants, maybe the definition of
ANOMALY_05000265 for BF561 should be changed to '(1)' instead.
Signed-off-by: Enrik Berkhan <Enrik.Berkhan@ge.com>
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin')
| -rw-r--r-- | arch/blackfin/mach-common/clocks-init.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/blackfin/mach-common/clocks-init.c b/arch/blackfin/mach-common/clocks-init.c index 9dddb6f8cc85..35393651359b 100644 --- a/arch/blackfin/mach-common/clocks-init.c +++ b/arch/blackfin/mach-common/clocks-init.c @@ -17,7 +17,7 @@ #define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */ #define PLL_CTL_VAL \ (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \ - (PLL_BYPASS << 8) | (ANOMALY_05000265 ? 0x8000 : 0)) + (PLL_BYPASS << 8) | (ANOMALY_05000305 ? 0 : 0x8000)) __attribute__((l1_text)) static void do_sync(void) |