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authorYash Shah2020-01-03 09:43:20 +0530
committerPaul Walmsley2020-01-03 00:56:23 -0800
commitcfda8617e22a8bf217a613d0b3ba3a38778443ba (patch)
tree85fbdb2001a712861d788616d17dc654e28740dd /arch/hexagon
parent0da310e82d3a9bff6ef6b0f2fbf45d1a05cc64fe (diff)
riscv: dts: Add DT support for SiFive L2 cache controller
Add the L2 cache controller DT node in SiFive FU540 soc-specific DT file Signed-off-by: Yash Shah <yash.shah@sifive.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
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