diff options
| author | James Bottomley | 2006-06-27 02:53:49 -0700 |
|---|---|---|
| committer | Linus Torvalds | 2006-06-27 17:32:38 -0700 |
| commit | 96c52749036eca2b131f435d3895a3c6aba92e76 (patch) | |
| tree | 77b92dfa86d4d81b3ee11f2517e118c6025026c6 /arch/i386/kernel/cpu | |
| parent | 4031ff388138b58e5cd472dccce38828bcb8c706 (diff) | |
[PATCH] fix subarchitecture breakage with CONFIG_SCHED_SMT
Commit 1e9f28fa1eb9773bf65bae08288c6a0a38eef4a7 ("[PATCH] sched: new
sched domain for representing multi-core") incorrectly made SCHED_SMT
and some of the structures it uses dependent on SMP.
However, this is wrong, the structures are only defined if X86_HT, so
SCHED_SMT has to depend on that as well.
The patch broke voyager, since it doesn't provide any of the multi-core
or hyperthreading structures.
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/i386/kernel/cpu')
| -rw-r--r-- | arch/i386/kernel/cpu/common.c | 2 | ||||
| -rw-r--r-- | arch/i386/kernel/cpu/intel_cacheinfo.c | 6 |
2 files changed, 4 insertions, 4 deletions
diff --git a/arch/i386/kernel/cpu/common.c b/arch/i386/kernel/cpu/common.c index 2fa401f19f37..70c87de582c7 100644 --- a/arch/i386/kernel/cpu/common.c +++ b/arch/i386/kernel/cpu/common.c @@ -294,7 +294,7 @@ void __cpuinit generic_identify(struct cpuinfo_x86 * c) if (c->x86 >= 0x6) c->x86_model += ((tfms >> 16) & 0xF) << 4; c->x86_mask = tfms & 15; -#ifdef CONFIG_SMP +#ifdef CONFIG_X86_HT c->apicid = phys_pkg_id((ebx >> 24) & 0xFF, 0); #else c->apicid = (ebx >> 24) & 0xFF; diff --git a/arch/i386/kernel/cpu/intel_cacheinfo.c b/arch/i386/kernel/cpu/intel_cacheinfo.c index f24a0145024c..8a92642ea590 100644 --- a/arch/i386/kernel/cpu/intel_cacheinfo.c +++ b/arch/i386/kernel/cpu/intel_cacheinfo.c @@ -261,7 +261,7 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c) unsigned int new_l1d = 0, new_l1i = 0; /* Cache sizes from cpuid(4) */ unsigned int new_l2 = 0, new_l3 = 0, i; /* Cache sizes from cpuid(4) */ unsigned int l2_id = 0, l3_id = 0, num_threads_sharing, index_msb; -#ifdef CONFIG_SMP +#ifdef CONFIG_X86_HT unsigned int cpu = (c == &boot_cpu_data) ? 0 : (c - cpu_data); #endif @@ -383,14 +383,14 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c) if (new_l2) { l2 = new_l2; -#ifdef CONFIG_SMP +#ifdef CONFIG_X86_HT cpu_llc_id[cpu] = l2_id; #endif } if (new_l3) { l3 = new_l3; -#ifdef CONFIG_SMP +#ifdef CONFIG_X86_HT cpu_llc_id[cpu] = l3_id; #endif } |