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| author | Thomas Bogendoerfer | 2020-08-24 18:32:43 +0200 |
|---|---|---|
| committer | Thomas Bogendoerfer | 2020-09-07 22:23:29 +0200 |
| commit | 802b83627f54d63d3d95d0285ec9a5d80be434c0 (patch) | |
| tree | 240f728d7f4923617f34fba529157606d5ac9b85 /arch/mips/Kconfig | |
| parent | 8c2ede45edbea7e970ea6bd171fc6afbec0761b3 (diff) | |
MIPS: Convert R4600_V1_INDEX_ICACHEOP into a config option
Use a new config option to enable R4600 V1 index I-cacheop workaround
and remove define from different war.h files.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/Kconfig')
| -rw-r--r-- | arch/mips/Kconfig | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 5f4c2d43c073..595916e504a3 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -638,6 +638,7 @@ config SGI_IP22 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN + select WAR_R4600_V1_INDEX_ICACHEOP select MIPS_L1_CACHE_SHIFT_7 help This are the SGI Indy, Challenge S and Indigo2, as well as certain @@ -2607,6 +2608,13 @@ config MIPS_ASID_BITS_VARIABLE config MIPS_CRC_SUPPORT bool +# R4600 erratum. Due to the lack of errata information the exact +# technical details aren't known. I've experimentally found that disabling +# interrupts during indexed I-cache flushes seems to be sufficient to deal +# with the issue. +config WAR_R4600_V1_INDEX_ICACHEOP + bool + # # - Highmem only makes sense for the 32-bit kernel. # - The current highmem code will only work properly on physically indexed |