diff options
| author | Hauke Mehrtens | 2010-02-20 19:51:20 +0100 |
|---|---|---|
| committer | Ralf Baechle | 2010-02-22 21:42:12 +0100 |
| commit | 84a6fcb368a080620d12fc4d79e07902dbee7335 (patch) | |
| tree | fc842c252eed342e5457b407dc78627ffaa7eb71 /arch/mips/bcm47xx | |
| parent | 52ab320ac560af3333191a473e56615fb48fff95 (diff) | |
MIPS: BCM47xx: Fix 128MB RAM support
Ignoring the last page when ddr size is 128M. Cached accesses to last page
is causing the processor to prefetch using address above 128M stepping out
of the DDR address space.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/981/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/bcm47xx')
| -rw-r--r-- | arch/mips/bcm47xx/prom.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c index c51405e57921..29d3cbf9555f 100644 --- a/arch/mips/bcm47xx/prom.c +++ b/arch/mips/bcm47xx/prom.c @@ -141,6 +141,14 @@ static __init void prom_init_mem(void) break; } + /* Ignoring the last page when ddr size is 128M. Cached + * accesses to last page is causing the processor to prefetch + * using address above 128M stepping out of the ddr address + * space. + */ + if (mem == 0x8000000) + mem -= 0x1000; + add_memory_region(0, mem, BOOT_MEM_RAM); } |