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authorLeonid Yegoshin2014-11-14 11:55:50 +0000
committerMarkos Chandras2015-02-17 15:37:29 +0000
commitb0ce4bd535a68e5814b8470f1f8a49771f37b0a2 (patch)
tree3ffd6805a81c1b5e36a027cb26587fde3ac52e84 /arch/mips/lib
parentfee313d4b880d4f68cd9d1ed013b128f836d3f21 (diff)
MIPS: lib: memcpy: Add MIPS R6 support
MIPS R6 does not support the unaligned load and store instructions so we add a special MIPS R6 case to copy one byte at a time if we need to read/write to unaligned memory addresses. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Diffstat (limited to 'arch/mips/lib')
-rw-r--r--arch/mips/lib/memcpy.S23
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/mips/lib/memcpy.S b/arch/mips/lib/memcpy.S
index 5d3238af9b5c..9245e1705e69 100644
--- a/arch/mips/lib/memcpy.S
+++ b/arch/mips/lib/memcpy.S
@@ -293,9 +293,14 @@
and t0, src, ADDRMASK
PREFS( 0, 2*32(src) )
PREFD( 1, 2*32(dst) )
+#ifndef CONFIG_CPU_MIPSR6
bnez t1, .Ldst_unaligned\@
nop
bnez t0, .Lsrc_unaligned_dst_aligned\@
+#else
+ or t0, t0, t1
+ bnez t0, .Lcopy_unaligned_bytes\@
+#endif
/*
* use delay slot for fall-through
* src and dst are aligned; need to compute rem
@@ -376,6 +381,7 @@
bne rem, len, 1b
.set noreorder
+#ifndef CONFIG_CPU_MIPSR6
/*
* src and dst are aligned, need to copy rem bytes (rem < NBYTES)
* A loop would do only a byte at a time with possible branch
@@ -477,6 +483,7 @@
bne len, rem, 1b
.set noreorder
+#endif /* !CONFIG_CPU_MIPSR6 */
.Lcopy_bytes_checklen\@:
beqz len, .Ldone\@
nop
@@ -504,6 +511,22 @@
.Ldone\@:
jr ra
nop
+
+#ifdef CONFIG_CPU_MIPSR6
+.Lcopy_unaligned_bytes\@:
+1:
+ COPY_BYTE(0)
+ COPY_BYTE(1)
+ COPY_BYTE(2)
+ COPY_BYTE(3)
+ COPY_BYTE(4)
+ COPY_BYTE(5)
+ COPY_BYTE(6)
+ COPY_BYTE(7)
+ ADD src, src, 8
+ b 1b
+ ADD dst, dst, 8
+#endif /* CONFIG_CPU_MIPSR6 */
.if __memcpy == 1
END(memcpy)
.set __memcpy, 0