diff options
| author | Thomas Gleixner | 2011-03-27 15:19:28 +0200 |
|---|---|---|
| committer | Thomas Gleixner | 2011-03-29 14:48:07 +0200 |
| commit | e4ec7989b4e55d9275ebac66230b7dac6dcb1fae (patch) | |
| tree | b42cd789681bada83b0051899ed66c1c0e2bbea2 /arch/mips/pnx8550 | |
| parent | 9efbc3fba2cd7f703b55d72e5168ed4348930442 (diff) | |
MIPS: Convert the irq functions to the new names
Scripted with coccinelle.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/mips/pnx8550')
| -rw-r--r-- | arch/mips/pnx8550/common/int.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/mips/pnx8550/common/int.c b/arch/mips/pnx8550/common/int.c index dbdc35c3531d..6b93c81779c1 100644 --- a/arch/mips/pnx8550/common/int.c +++ b/arch/mips/pnx8550/common/int.c @@ -183,7 +183,7 @@ void __init arch_init_irq(void) int configPR; for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) - set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &level_irq_type, handle_level_irq); /* init of GIC/IPC interrupts */ /* should be done before cp0 since cp0 init enables the GIC int */ @@ -206,7 +206,7 @@ void __init arch_init_irq(void) /* mask/priority is still 0 so we will not get any * interrupts until it is unmasked */ - set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &level_irq_type, handle_level_irq); } /* Priority level 0 */ @@ -215,20 +215,20 @@ void __init arch_init_irq(void) /* Set int vector table address */ PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0; - set_irq_chip_and_handler(MIPS_CPU_GIC_IRQ, &level_irq_type, + irq_set_chip_and_handler(MIPS_CPU_GIC_IRQ, &level_irq_type, handle_level_irq); setup_irq(MIPS_CPU_GIC_IRQ, &gic_action); /* init of Timer interrupts */ for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++) - set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); + irq_set_chip_and_handler(i, &level_irq_type, handle_level_irq); /* Stop Timer 1-3 */ configPR = read_c0_config7(); configPR |= 0x00000038; write_c0_config7(configPR); - set_irq_chip_and_handler(MIPS_CPU_TIMER_IRQ, &level_irq_type, + irq_set_chip_and_handler(MIPS_CPU_TIMER_IRQ, &level_irq_type, handle_level_irq); setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action); } |