diff options
| author | John Crispin | 2016-12-20 19:12:42 +0100 |
|---|---|---|
| committer | Ralf Baechle | 2017-01-03 16:34:47 +0100 |
| commit | 16eccef68f21b729d18573a36eef41053a5f35bd (patch) | |
| tree | 7e3bfa3e085a2d833d598a81b7c02fd3b9bc62d4 /arch/mips/ralink | |
| parent | 2517caf19dbfac3b39f2db5500c5fd03c4370e81 (diff) | |
MIPS: ralink: Add missing pinmux.
The mt7620 has a pin that can be used to generate an external reference
clock. The pinmux setup was missing the definition of said pin. This patch
adds it.
Signed-off-by: John Crispin <john@phrozen.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14898/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/ralink')
| -rw-r--r-- | arch/mips/ralink/mt7620.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c index 6f0fdfd1e32a..2503878824b8 100644 --- a/arch/mips/ralink/mt7620.c +++ b/arch/mips/ralink/mt7620.c @@ -55,7 +55,10 @@ static int dram_type; static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) }; static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) }; static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) }; -static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) }; +static struct rt2880_pmx_func mdio_grp[] = { + FUNC("mdio", MT7620_GPIO_MODE_MDIO, 22, 2), + FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2), +}; static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) }; static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) }; static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) }; @@ -92,7 +95,8 @@ static struct rt2880_pmx_group mt7620a_pinmux_data[] = { GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1), GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK, MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT), - GRP("mdio", mdio_grp, 1, MT7620_GPIO_MODE_MDIO), + GRP_G("mdio", mdio_grp, MT7620_GPIO_MODE_MDIO_MASK, + MT7620_GPIO_MODE_MDIO_GPIO, MT7620_GPIO_MODE_MDIO_SHIFT), GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1), GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK), GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK, |