diff options
| author | Huacai Chen | 2020-05-23 15:56:34 +0800 |
|---|---|---|
| committer | Paolo Bonzini | 2020-06-04 13:49:04 -0400 |
| commit | 52c07e1cbb6e16a0fe70646b4bc63f714caa0f3b (patch) | |
| tree | 1a65559ce18cb72b3824b3b97691eaa47ef4403e /arch/mips | |
| parent | 3210e2c279fee1076978b49988acdd935a6f7435 (diff) | |
KVM: MIPS: Use root tlb to control guest's CCA for Loongson-3
KVM guest has two levels of address translation: guest tlb translates
GVA to GPA, and root tlb translates GPA to HPA. By default guest's CCA
is controlled by guest tlb, but Loongson-3 maintains all cache coherency
by hardware (including multi-core coherency and I/O DMA coherency) so it
prefers all guest mappings be cacheable mappings. Thus, we use root tlb
to control guest's CCA for Loongson-3.
Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <1590220602-3547-8-git-send-email-chenhc@lemote.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/kvm/vz.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/mips/kvm/vz.c b/arch/mips/kvm/vz.c index 6e1b380e0b9c..6e62154ed09b 100644 --- a/arch/mips/kvm/vz.c +++ b/arch/mips/kvm/vz.c @@ -2871,6 +2871,12 @@ static int kvm_vz_hardware_enable(void) if (cpu_has_guestctl2) clear_c0_guestctl2(0x3f << 10); +#ifdef CONFIG_CPU_LOONGSON64 + /* Control guest CCA attribute */ + if (cpu_has_csr()) + csr_writel(csr_readl(0xffffffec) | 0x1, 0xffffffec); +#endif + return 0; } |