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authorDeng-Cheng Zhu2014-02-10 09:48:52 -0800
committerRalf Baechle2014-03-31 18:17:12 +0200
commit6b0b84295c4a82c89de64b80923e9d975e9249ed (patch)
treeef22454b20797f00d8dfcd40713c07db43949270 /arch/mips
parent823cf3cdd7a8612caf9542ef36228e5639e33738 (diff)
MIPS: perf: Rename 74K event/cache maps in preparation for Aptiv support
74K/proAptiv share the same event/cache maps. So it's better to change the names of the existing mipsxx74Kcore_[event|cache]_map. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Reviewed-by: Markos Chandras <Markos.Chandras@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Steven.Hill@imgtec.com Patchwork: https://patchwork.linux-mips.org/patch/6526/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/kernel/perf_event_mipsxx.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index 17594b81a5d2..d5294cc7a6ac 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -815,7 +815,7 @@ static const struct mips_perf_event mipsxxcore_event_map
};
/* 74K core has different branch event code. */
-static const struct mips_perf_event mipsxx74Kcore_event_map
+static const struct mips_perf_event mipsxxcore_event_map2
[PERF_COUNT_HW_MAX] = {
[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
@@ -931,7 +931,7 @@ static const struct mips_perf_event mipsxxcore_cache_map
};
/* 74K core has completely different cache event map. */
-static const struct mips_perf_event mipsxx74Kcore_cache_map
+static const struct mips_perf_event mipsxxcore_cache_map2
[PERF_COUNT_HW_CACHE_MAX]
[PERF_COUNT_HW_CACHE_OP_MAX]
[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
@@ -1577,8 +1577,8 @@ init_hw_perf_events(void)
break;
case CPU_74K:
mipspmu.name = "mips/74K";
- mipspmu.general_event_map = &mipsxx74Kcore_event_map;
- mipspmu.cache_event_map = &mipsxx74Kcore_cache_map;
+ mipspmu.general_event_map = &mipsxxcore_event_map2;
+ mipspmu.cache_event_map = &mipsxxcore_cache_map2;
break;
case CPU_1004K:
mipspmu.name = "mips/1004K";