diff options
| author | Álvaro Fernández Rojas | 2020-06-17 12:50:39 +0200 |
|---|---|---|
| committer | Thomas Bogendoerfer | 2020-11-17 21:53:03 +0100 |
| commit | 7acf84e87857721d66a1ba800c2c50669089f43d (patch) | |
| tree | 6b644c6cc10cf66ed9a05502b8469f7e557908e2 /arch/mips | |
| parent | 226383600be58dcf2e070e4ac8a371640024fe54 (diff) | |
mips: bmips: dts: add BCM6368 reset controller support
BCM6368 SoCs have a reset controller for certain components.
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/boot/dts/brcm/bcm6368.dtsi | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/mips/boot/dts/brcm/bcm6368.dtsi b/arch/mips/boot/dts/brcm/bcm6368.dtsi index 449c167dd892..52c19f40b9cc 100644 --- a/arch/mips/boot/dts/brcm/bcm6368.dtsi +++ b/arch/mips/boot/dts/brcm/bcm6368.dtsi @@ -70,6 +70,12 @@ mask = <0x1>; }; + periph_rst: reset-controller@10000010 { + compatible = "brcm,bcm6345-reset"; + reg = <0x10000010 0x4>; + #reset-cells = <1>; + }; + periph_intc: interrupt-controller@10000020 { compatible = "brcm,bcm6345-l1-intc"; reg = <0x10000020 0x10>, |