diff options
| author | David Howells | 2008-11-12 15:35:50 +0000 |
|---|---|---|
| committer | Linus Torvalds | 2008-11-12 10:41:18 -0800 |
| commit | bd9384a9fdd6c15da6b01b2844c3471d07a45d64 (patch) | |
| tree | ea78ffcb7039b170dd129a890eb0ded9b17207a7 /arch/mn10300 | |
| parent | d3bd462865421dd8be310fac2d2f6da6069f9679 (diff) | |
MN10300: Don't handle misaligned loading and storing of SP
Don't handle the misaligned loading and storing of the SP register as in C code
that's most certainly a compiler bug.
Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'arch/mn10300')
| -rw-r--r-- | arch/mn10300/mm/misalignment.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/mn10300/mm/misalignment.c b/arch/mn10300/mm/misalignment.c index e247a6e1b8de..7b670a3d7659 100644 --- a/arch/mn10300/mm/misalignment.c +++ b/arch/mn10300/mm/misalignment.c @@ -204,8 +204,6 @@ static const struct mn10300_opcode mn10300_opcodes[] = { { "mov", 0xf81000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}}, { "mov", 0xf82000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8,AM0), AN1}}, { "mov", 0xf83000, 0xfff000, 0, FMT_D1, 0, {AM1, MEM2(SD8, AN0)}}, -{ "mov", 0xf8f000, 0xfffc00, 0, FMT_D1, AM33, {MEM2(SD8, AM0), SP}}, -{ "mov", 0xf8f400, 0xfffc00, 0, FMT_D1, AM33, {SP, MEM2(SD8, AN0)}}, { "mov", 0xf90a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}}, { "mov", 0xf91a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}}, { "mov", 0xf96a00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}}, |