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authorJohn David Anglin2020-07-28 19:13:20 +0200
committerHelge Deller2020-07-28 19:29:38 +0200
commite72b23dec1da5e62a0090c5da1d926778284e230 (patch)
tree715b1334dd13ee9dbea9d960f25cef1addbce778 /arch/parisc
parent157e9afcc4fa25068b0e8743bc254a9b56010e13 (diff)
parisc: Do not use an ordered store in pa_tlb_lock()
No need to use an ordered store in pa_tlb_lock() and update the comment regarng usage of the sid register to unlocak a spinlock in tlb_unlock0(). Signed-off-by: John David Anglin <dave.anglin@bell.net> Signed-off-by: Helge Deller <deller@gmx.de> Cc: <stable@vger.kernel.org> # v5.0+
Diffstat (limited to 'arch/parisc')
-rw-r--r--arch/parisc/kernel/entry.S9
1 files changed, 7 insertions, 2 deletions
diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S
index 06455f1a40f5..519f9056fd00 100644
--- a/arch/parisc/kernel/entry.S
+++ b/arch/parisc/kernel/entry.S
@@ -455,7 +455,7 @@
LDREG 0(\ptp),\pte
bb,<,n \pte,_PAGE_PRESENT_BIT,3f
b \fault
- stw,ma \spc,0(\tmp)
+ stw \spc,0(\tmp)
99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
#endif
2: LDREG 0(\ptp),\pte
@@ -463,7 +463,12 @@
3:
.endm
- /* Release pa_tlb_lock lock without reloading lock address. */
+ /* Release pa_tlb_lock lock without reloading lock address.
+ Note that the values in the register spc are limited to
+ NR_SPACE_IDS (262144). Thus, the stw instruction always
+ stores a nonzero value even when register spc is 64 bits.
+ We use an ordered store to ensure all prior accesses are
+ performed prior to releasing the lock. */
.macro tlb_unlock0 spc,tmp
#ifdef CONFIG_SMP
98: or,COND(=) %r0,\spc,%r0