diff options
| author | Linus Torvalds | 2011-03-18 06:31:43 -0700 |
|---|---|---|
| committer | Linus Torvalds | 2011-03-18 06:31:43 -0700 |
| commit | 0a95d92c0054e74fb79607ac2df958b7bf295706 (patch) | |
| tree | e2c5f836e799dcfd72904949be47595af91432e7 /arch/powerpc/mm | |
| parent | 08351fc6a75731226e1112fc7254542bd3a2912e (diff) | |
| parent | 831532035b12a5f7b600515a6f4da0b207b82d6e (diff) | |
Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (62 commits)
powerpc/85xx: Fix signedness bug in cache-sram
powerpc/fsl: 85xx: document cache sram bindings
powerpc/fsl: define binding for fsl mpic interrupt controllers
powerpc/fsl_msi: Handle msi-available-ranges better
drivers/serial/ucc_uart.c: Add of_node_put to avoid memory leak
powerpc/85xx: Fix SPE float to integer conversion failure
powerpc/85xx: Update sata controller compatible for p1022ds board
ATA: Add FSL sata v2 controller support
powerpc/mpc8xxx_gpio: simplify searching for 'fsl, qoriq-gpio' compatiable
powerpc/8xx: remove obsolete mgsuvd board
powerpc/82xx: rename and update mgcoge board support
powerpc/83xx: rename and update kmeter1
powerpc/85xx: Workaroudn e500 CPU erratum A005
powerpc/fsl_pci: Add support for FSL PCIe controllers v2.x
powerpc/85xx: Fix writing to spin table 'cpu-release-addr' on ppc64e
powerpc/pseries: Disable MSI using new interface if possible
powerpc: Enable GENERIC_HARDIRQS_NO_DEPRECATED.
powerpc: core irq_data conversion.
powerpc: sysdev/xilinx_intc irq_data conversion.
powerpc: sysdev/uic irq_data conversion.
...
Fix up conflicts in arch/powerpc/sysdev/fsl_msi.c (due to getting rid of
of_platform_driver in arch/powerpc)
Diffstat (limited to 'arch/powerpc/mm')
| -rw-r--r-- | arch/powerpc/mm/init_32.c | 2 | ||||
| -rw-r--r-- | arch/powerpc/mm/tlb_nohash_low.S | 35 |
2 files changed, 36 insertions, 1 deletions
diff --git a/arch/powerpc/mm/init_32.c b/arch/powerpc/mm/init_32.c index 742da43b4ab6..d65b591e5556 100644 --- a/arch/powerpc/mm/init_32.c +++ b/arch/powerpc/mm/init_32.c @@ -148,7 +148,7 @@ void __init MMU_init(void) lowmem_end_addr = memstart_addr + total_lowmem; #ifndef CONFIG_HIGHMEM total_memory = total_lowmem; - memblock_enforce_memory_limit(lowmem_end_addr); + memblock_enforce_memory_limit(total_lowmem); memblock_analyze(); #endif /* CONFIG_HIGHMEM */ } diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S index af405eefe48d..7c63c0ed4f1b 100644 --- a/arch/powerpc/mm/tlb_nohash_low.S +++ b/arch/powerpc/mm/tlb_nohash_low.S @@ -189,6 +189,13 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x) blr #ifdef CONFIG_PPC_47x + +/* + * 47x variant of icbt + */ +# define ICBT(CT,RA,RB) \ + .long 0x7c00002c | ((CT) << 21) | ((RA) << 16) | ((RB) << 11) + /* * _tlbivax_bcast is only on 47x. We don't bother doing a runtime * check though, it will blow up soon enough if we mistakenly try @@ -206,7 +213,35 @@ _GLOBAL(_tlbivax_bcast) isync eieio tlbsync +BEGIN_FTR_SECTION + b 1f +END_FTR_SECTION_IFSET(CPU_FTR_476_DD2) + sync + wrtee r10 + blr +/* + * DD2 HW could hang if in instruction fetch happens before msync completes. + * Touch enough instruction cache lines to ensure cache hits + */ +1: mflr r9 + bl 2f +2: mflr r6 + li r7,32 + ICBT(0,r6,r7) /* touch next cache line */ + add r6,r6,r7 + ICBT(0,r6,r7) /* touch next cache line */ + add r6,r6,r7 + ICBT(0,r6,r7) /* touch next cache line */ sync + nop + nop + nop + nop + nop + nop + nop + nop + mtlr r9 wrtee r10 blr #endif /* CONFIG_PPC_47x */ |