diff options
| author | Kumar Gala | 2009-05-08 15:05:23 -0500 |
|---|---|---|
| committer | Kumar Gala | 2009-05-19 00:50:44 -0500 |
| commit | 54c181935d2a2d46a1b2f00cbb25acc35e4f5ee2 (patch) | |
| tree | bc2dfbf4f9199d8735fcca96c5d3cb2c6aea56cb /arch/powerpc/sysdev/fsl_pci.h | |
| parent | 01af9507ff36578dad89b1cc88ff37ac18e719cb (diff) | |
powerpc/fsl: Setup PCI inbound window based on actual amount of memory
Previouslly we just always set the inbound window to 2G. This was
broken for systems with >2G. If a system has >=4G we will need
SWIOTLB support to handle that case.
We now allocate PCICSRBAR/PEXCSRBAR right below the lowest PCI outbound
address for MMIO or the 4G boundary (if the lowest PCI address is above
4G).
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/sysdev/fsl_pci.h')
| -rw-r--r-- | arch/powerpc/sysdev/fsl_pci.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h index 13f30c2a61e7..a9d8bbebed80 100644 --- a/arch/powerpc/sysdev/fsl_pci.h +++ b/arch/powerpc/sysdev/fsl_pci.h @@ -16,7 +16,11 @@ #define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */ #define PCIE_LTSSM_L0 0x16 /* L0 state */ -#define PIWAR_2G 0xa0f5501e /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */ +#define PIWAR_EN 0x80000000 /* Enable */ +#define PIWAR_PF 0x20000000 /* prefetch */ +#define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */ +#define PIWAR_READ_SNOOP 0x00050000 +#define PIWAR_WRITE_SNOOP 0x00005000 /* PCI/PCI Express outbound window reg */ struct pci_outbound_window_regs { |