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authorJulia Lawall2022-04-30 20:56:54 +0200
committerMichael Ellerman2022-05-05 22:12:44 +1000
commit1fd02f6605b855b4af2883f29a2abc88bdf17857 (patch)
tree964bfb2ca78a94aee8dcd37dfdce5b6fbfa3f501 /arch/powerpc/sysdev/mpic_u3msi.c
parentc14d31bae372e050b053f2511fb3f0f90c27e4f9 (diff)
powerpc: fix typos in comments
Various spelling mistakes in comments. Detected with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220430185654.5855-1-Julia.Lawall@inria.fr
Diffstat (limited to 'arch/powerpc/sysdev/mpic_u3msi.c')
-rw-r--r--arch/powerpc/sysdev/mpic_u3msi.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/sysdev/mpic_u3msi.c b/arch/powerpc/sysdev/mpic_u3msi.c
index 3f4841dfefb5..73d129594078 100644
--- a/arch/powerpc/sysdev/mpic_u3msi.c
+++ b/arch/powerpc/sysdev/mpic_u3msi.c
@@ -78,7 +78,7 @@ static u64 find_u4_magic_addr(struct pci_dev *pdev, unsigned int hwirq)
/* U4 PCIe MSIs need to write to the special register in
* the bridge that generates interrupts. There should be
- * theorically a register at 0xf8005000 where you just write
+ * theoretically a register at 0xf8005000 where you just write
* the MSI number and that triggers the right interrupt, but
* unfortunately, this is busted in HW, the bridge endian swaps
* the value and hits the wrong nibble in the register.