diff options
| author | Gavin Shan | 2013-11-12 14:49:21 +0800 |
|---|---|---|
| committer | Benjamin Herrenschmidt | 2013-11-21 10:33:35 +1100 |
| commit | bf898ec5cbd33be11147743bee27b66b10cb2f85 (patch) | |
| tree | bc913203917845a6e381d22598c313899f184c23 /arch/powerpc | |
| parent | b4789b8e6be3151a955ade74872822f30e8cd914 (diff) | |
powerpc/eeh: Enable PCI_COMMAND_MASTER for PCI bridges
On PHB3, we will fail to fetch IODA tables without PCI_COMMAND_MASTER
on PCI bridges. According to one experiment I had, the MSIx interrupts
didn't raise from the adapter without the bit applied to all upstream
PCI bridges including root port of the adapter. The patch forces to
have that bit enabled accordingly.
Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
CC: <stable@vger.kernel.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc')
| -rw-r--r-- | arch/powerpc/kernel/eeh.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/powerpc/kernel/eeh.c b/arch/powerpc/kernel/eeh.c index 671302065347..4bd687d5e7aa 100644 --- a/arch/powerpc/kernel/eeh.c +++ b/arch/powerpc/kernel/eeh.c @@ -686,6 +686,15 @@ void eeh_save_bars(struct eeh_dev *edev) for (i = 0; i < 16; i++) eeh_ops->read_config(dn, i * 4, 4, &edev->config_space[i]); + + /* + * For PCI bridges including root port, we need enable bus + * master explicitly. Otherwise, it can't fetch IODA table + * entries correctly. So we cache the bit in advance so that + * we can restore it after reset, either PHB range or PE range. + */ + if (edev->mode & EEH_DEV_BRIDGE) + edev->config_space[1] |= PCI_COMMAND_MASTER; } /** |