diff options
| author | Heiko Stuebner | 2022-05-11 21:29:21 +0200 |
|---|---|---|
| committer | Palmer Dabbelt | 2022-05-11 21:36:33 -0700 |
| commit | a35707c3d850dda0ceefb75b1b3bd191921d5765 (patch) | |
| tree | 00188dae0c8c04eabd08b304924d1d84c92acbd1 /arch/riscv/Kconfig | |
| parent | 1745cfafebdfb017f6871c80f9894910a76373a4 (diff) | |
riscv: add memory-type errata for T-Head
Some current cpus based on T-Head cores implement memory-types
way different than described in the svpbmt spec even going
so far as using PTE bits marked as reserved.
Add the T-Head vendor-id and necessary errata code to
replace the affected instructions.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20220511192921.2223629-13-heiko@sntech.de
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/Kconfig')
| -rw-r--r-- | arch/riscv/Kconfig | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 3935358c03f5..d08584681216 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -333,6 +333,12 @@ config RISCV_ALTERNATIVE code patching is performed once in the boot stages. It means that the overhead from this mechanism is just taken once. +config RISCV_ALTERNATIVE_EARLY + bool + depends on RISCV_ALTERNATIVE + help + Allows early patching of the kernel for special errata + config RISCV_ISA_C bool "Emit compressed instructions when building Linux" default y |