diff options
| author | Conor Dooley | 2022-09-27 12:19:23 +0100 |
|---|---|---|
| committer | Conor Dooley | 2022-09-27 18:53:59 +0100 |
| commit | 6c1193301791d3fcc0ad9ff3b861a8216e00773b (patch) | |
| tree | 26b3a0c7cb357b46be33563cd3b974663b0486f6 /arch/riscv/boot | |
| parent | d49166646e44064b694a2e631fcdba4f814746d9 (diff) | |
riscv: dts: microchip: update memory configuration for v2022.10
In the v2022.10 reference design, the seg registers are going to be
changed, resulting in a required change to the memory map in Linux.
A small 4M reservation is made at the end of 32-bit DDR to provide some
memory for the HSS to use, so that it can cache its payload.bin between
reboots of a specific context.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'arch/riscv/boot')
| -rw-r--r-- | arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts index 42d350fe6c6b..31f88cb4d5e5 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts @@ -33,15 +33,26 @@ ddrc_cache_lo: memory@80000000 { device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x2e000000>; + reg = <0x0 0x80000000 0x0 0x40000000>; status = "okay"; }; ddrc_cache_hi: memory@1000000000 { device_type = "memory"; - reg = <0x10 0x0 0x0 0x40000000>; + reg = <0x10 0x40000000 0x0 0x40000000>; status = "okay"; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hss_payload: region@BFC00000 { + reg = <0x0 0xBFC00000 0x0 0x400000>; + no-map; + }; + }; }; &core_pwm0 { |