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authorConor Dooley2022-09-27 12:19:20 +0100
committerConor Dooley2022-09-27 18:53:58 +0100
commitfa52935abef422d119dda3c10c02787a86e6289d (patch)
treed1facd93dd3ecc68d2657a9175c9f0191662a7da /arch/riscv/boot
parentab291621a8b85269496ae9a964b6d49cd1e030c8 (diff)
riscv: dts: microchip: reduce the fic3 clock rate
For the v2022.09 release of the reference design, the fic3 clock rate been reduced from 62.5 MHz to 50 MHz as it allows timing to be closed significantly more quickly by customers who chose to build the reference design themselves. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'arch/riscv/boot')
-rw-r--r--arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
index 35030ea330ee..b6bfe177ccb2 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
@@ -29,7 +29,7 @@
fabric_clk3: fabric-clk3 {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <62500000>;
+ clock-frequency = <50000000>;
};
fabric_clk1: fabric-clk1 {