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authorPalmer Dabbelt2022-12-01 11:38:39 -0800
committerPalmer Dabbelt2022-12-01 11:38:39 -0800
commit39cefc5f6cd25d555e0455b24810e9aff365b8d6 (patch)
tree3f5ae903747a2bec6fab24ea9de151ddbdf766cf /arch/riscv/include
parentd556a9aeb62a6cd44aa05aeadcc48245da0a1939 (diff)
parent7e1864332fbc1b993659eab7974da9fe8bf8c128 (diff)
RISC-V: Fix a race condition during kernel stack overflow
This fixes a concrete bug but is also the basis for some cleanup work, so I'm merging it based on the offending commit in order to minimize future conflicts. * commit '7e1864332fbc1b993659eab7974da9fe8bf8c128': riscv: fix race when vmap stack overflow
Diffstat (limited to 'arch/riscv/include')
-rw-r--r--arch/riscv/include/asm/asm.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h
index 1b471ff73178..816e753de636 100644
--- a/arch/riscv/include/asm/asm.h
+++ b/arch/riscv/include/asm/asm.h
@@ -23,6 +23,7 @@
#define REG_L __REG_SEL(ld, lw)
#define REG_S __REG_SEL(sd, sw)
#define REG_SC __REG_SEL(sc.d, sc.w)
+#define REG_AMOSWAP_AQ __REG_SEL(amoswap.d.aq, amoswap.w.aq)
#define REG_ASM __REG_SEL(.dword, .word)
#define SZREG __REG_SEL(8, 4)
#define LGREG __REG_SEL(3, 2)