diff options
| author | Christoph Hellwig | 2018-01-09 15:00:34 +0100 |
|---|---|---|
| committer | Palmer Dabbelt | 2018-01-30 19:16:17 -0800 |
| commit | 4889dec6c87d90619cc1e8436327b91f4bb0e467 (patch) | |
| tree | 73a29b38f16dda0f633ed1ce3f4e3348ae200b83 /arch/riscv/include | |
| parent | 7549cdf59d9fafbaab42650375c29c64c16aa270 (diff) | |
riscv: inline set_pgdir into its only caller
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'arch/riscv/include')
| -rw-r--r-- | arch/riscv/include/asm/mmu_context.h | 17 |
1 files changed, 6 insertions, 11 deletions
diff --git a/arch/riscv/include/asm/mmu_context.h b/arch/riscv/include/asm/mmu_context.h index d30f0c54b8b2..336d60ec5698 100644 --- a/arch/riscv/include/asm/mmu_context.h +++ b/arch/riscv/include/asm/mmu_context.h @@ -39,16 +39,6 @@ static inline void destroy_context(struct mm_struct *mm) { } -static inline void set_pgdir(pgd_t *pgd) -{ - /* - * Use the old spbtr name instead of using the current satp - * name to support binutils 2.29 which doesn't know about the - * privileged ISA 1.10 yet. - */ - csr_write(sptbr, virt_to_pfn(next->pgd) | SATP_MODE); -} - /* * When necessary, performs a deferred icache flush for the given MM context, * on the local CPU. RISC-V has no direct mechanism for instruction cache @@ -93,7 +83,12 @@ static inline void switch_mm(struct mm_struct *prev, cpumask_clear_cpu(cpu, mm_cpumask(prev)); cpumask_set_cpu(cpu, mm_cpumask(next)); - set_pgdir(next->pgd); + /* + * Use the old spbtr name instead of using the current satp + * name to support binutils 2.29 which doesn't know about the + * privileged ISA 1.10 yet. + */ + csr_write(sptbr, virt_to_pfn(next->pgd) | SATP_MODE); local_flush_tlb_all(); flush_icache_deferred(next); |