diff options
| author | Akira Tsukamoto | 2021-07-20 17:51:45 +0900 |
|---|---|---|
| committer | Palmer Dabbelt | 2021-07-23 17:49:01 -0700 |
| commit | 22b5f16ffeff38938ad7420a2bfa3c281c36fd17 (patch) | |
| tree | bea1759072fae25d84958e39380549875bdbc553 /arch/riscv/lib | |
| parent | 6010d300f9f7e16d1bf327b4730bcd0c0886d9e6 (diff) | |
riscv: __asm_copy_to-from_user: Fix: fail on RV32
Had a bug when converting bytes to bits when the cpu was rv32.
The a3 contains the number of bytes and multiple of 8
would be the bits. The LGREG is holding 2 for RV32 and 3 for
RV32, so to achieve multiple of 8 it must always be constant 3.
The 2 was mistakenly used for rv32.
Signed-off-by: Akira Tsukamoto <akira.tsukamoto@gmail.com>
Fixes: ca6eaaa210de ("riscv: __asm_copy_to-from_user: Optimize unaligned memory access and pipeline stall")
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'arch/riscv/lib')
| -rw-r--r-- | arch/riscv/lib/uaccess.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/lib/uaccess.S b/arch/riscv/lib/uaccess.S index 8bbeca89a93f..279876821969 100644 --- a/arch/riscv/lib/uaccess.S +++ b/arch/riscv/lib/uaccess.S @@ -125,7 +125,7 @@ ENTRY(__asm_copy_from_user) * t3 - prev shift * t4 - current shift */ - slli t3, a3, LGREG + slli t3, a3, 3 /* converting bytes in a3 to bits */ li a5, SZREG*8 sub t4, a5, t3 |