diff options
| author | Anup Patel | 2022-11-14 14:35:34 +0530 |
|---|---|---|
| committer | Greg Kroah-Hartman | 2022-12-31 13:32:37 +0100 |
| commit | e395fdfec46d4adbee0e849e9feaa706871da2af (patch) | |
| tree | 5b246d43bd66a7e6ec1072c74f83d7710f7010b8 /arch/riscv/mm/physaddr.c | |
| parent | eced7ec0cd894972f819d05ad2ef0bc57c585873 (diff) | |
RISC-V: Fix MEMREMAP_WB for systems with Svpbmt
[ Upstream commit b91676fc16cd384a81e3af52c641aa61985cc231 ]
Currently, the memremap() called with MEMREMAP_WB maps memory using
the generic ioremap() function which breaks on system with Svpbmt
because memory mapped using _PAGE_IOREMAP page attributes is treated
as strongly-ordered non-cacheable IO memory.
To address this, we implement RISC-V specific arch_memremap_wb()
which maps memory using _PAGE_KERNEL page attributes resulting in
write-back cacheable mapping on systems with Svpbmt.
Fixes: ff689fd21cb1 ("riscv: add RISC-V Svpbmt extension support")
Co-developed-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20221114090536.1662624-2-apatel@ventanamicro.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'arch/riscv/mm/physaddr.c')
0 files changed, 0 insertions, 0 deletions