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author | Linus Torvalds | 2024-09-17 10:53:21 +0200 |
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committer | Linus Torvalds | 2024-09-17 10:53:21 +0200 |
commit | 38ea77ab07480fa57a80bbdc2706ab2807ebc9e6 (patch) | |
tree | c7cc5c01caf800e06939eb7e5e77686dc61b0606 /arch/riscv | |
parent | b8979c6b4d0d1b36e94f5bc483fd86e38107e554 (diff) | |
parent | 7eee0f8bbd1b6946236624d25a938cb34c1ba2a9 (diff) |
Merge tag 'soc-defconfig-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC defconfig updates from Arnd Bergmann:
"The updates to the defconfig files are fairly small, enabling drivers
for eight of the arm and riscv based platforms"
* tag 'soc-defconfig-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
arm64: defconfig: enable mt8365 sound
riscv: defconfig: Enable pinctrl support for CV18XX Series SoC
arm64: defconfig: Enable ADP5585 GPIO and PWM drivers
arm64: defconfig: Enable Tegra194 PCIe Endpoint
arm64: defconfig: Enable E5010 JPEG Encoder
riscv: defconfig: sophgo: enable clks for sg2042
arm64: defconfig: build CONFIG_REGULATOR_QCOM_REFGEN as module
ARM: configs: at91: enable config flags for sam9x7 SoC family
arm64: defconfig: Enable R-Car Ethernet-TSN support
ARM: shmobile: defconfig: Enable slab hardening and kmalloc buckets
arm64: defconfig: Enable AK4619 codec support
Diffstat (limited to 'arch/riscv')
-rw-r--r-- | arch/riscv/configs/defconfig | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 0d678325444f..ee978cc74673 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -167,6 +167,10 @@ CONFIG_SPI_RSPI=m CONFIG_SPI_SIFIVE=y CONFIG_SPI_SUN6I=y # CONFIG_PTP_1588_CLOCK is not set +CONFIG_PINCTRL_SOPHGO_CV1800B=y +CONFIG_PINCTRL_SOPHGO_CV1812H=y +CONFIG_PINCTRL_SOPHGO_SG2000=y +CONFIG_PINCTRL_SOPHGO_SG2002=y CONFIG_GPIO_SIFIVE=y CONFIG_POWER_RESET_GPIO_RESTART=y CONFIG_SENSORS_SFCTEMP=m @@ -249,6 +253,9 @@ CONFIG_VIRTIO_BALLOON=y CONFIG_VIRTIO_INPUT=y CONFIG_VIRTIO_MMIO=y CONFIG_CLK_SOPHGO_CV1800=y +CONFIG_CLK_SOPHGO_SG2042_PLL=y +CONFIG_CLK_SOPHGO_SG2042_CLKGEN=y +CONFIG_CLK_SOPHGO_SG2042_RPGATE=y CONFIG_SUN8I_DE2_CCU=m CONFIG_RENESAS_OSTM=y CONFIG_SUN50I_IOMMU=y |