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author | Linus Torvalds | 2022-10-09 13:13:48 -0700 |
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committer | Linus Torvalds | 2022-10-09 13:13:48 -0700 |
commit | 57c92724c8c19fc1b099826610fdb51985de12ba (patch) | |
tree | 63aa1e7afa21483a60aa16af27122aaec7567bd1 /arch/riscv | |
parent | ef688f8b8cd3eb20547a6543f03e3d8952b87769 (diff) | |
parent | adc4cefae9cfafc1c88b789021266d6f09a0ecef (diff) |
Merge tag 'microblaze-v6.1' of git://git.monstr.eu/linux-2.6-microblaze
Pull microblaze updates from Michal Simek:
"This adds architecture support for error injection which can be done
only via local memory (BRAM) with enabling path for recovery after
reset.
These patches targets Triple Modular Redundacy (TMR) configuration
where 3 Microblazes are running in parallel with monitoring logic.
When an error happens (or is injected) system goes to break handler
with full CPU reset and system recovery back to origin context. More
information can be found at [1]"
Link: https://www.xilinx.com/content/dam/xilinx/support/documents/ip_documentation/tmr/v1_0/pg268-tmr.pdf [1]
* tag 'microblaze-v6.1' of git://git.monstr.eu/linux-2.6-microblaze:
microblaze: Add support for error injection
microblaze: Add custom break vector handler for mb manager
microblaze: Add xmb_manager_register function
Diffstat (limited to 'arch/riscv')
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