diff options
| author | David S. Miller | 2018-10-14 20:22:28 -0700 |
|---|---|---|
| committer | David S. Miller | 2018-10-14 20:22:28 -0700 |
| commit | d1f1f98c6d1708a90436e1a3b2aff5e93946731b (patch) | |
| tree | ae685ee0f6253c4193228830230e5a45489a3c64 /arch/sparc | |
| parent | b3e1eb8e7ac9aaa283989496651d99267c4cad6c (diff) | |
sparc64: Set %l4 properly on trap return after handling signals.
If we did some signal processing, we have to reload the pt_regs
tstate register because it's value may have changed.
In doing so we also have to extract the %pil value contained in there
anre load that into %l4.
This value is at bit 20 and thus needs to be shifted down before we
later write it into the %pil register.
Most of the time this is harmless as we are returning to userspace
and the %pil is zero for that case.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc')
| -rw-r--r-- | arch/sparc/kernel/rtrap_64.S | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/sparc/kernel/rtrap_64.S b/arch/sparc/kernel/rtrap_64.S index f6528884a2c8..4073e2b87dd0 100644 --- a/arch/sparc/kernel/rtrap_64.S +++ b/arch/sparc/kernel/rtrap_64.S @@ -84,8 +84,9 @@ __handle_signal: ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1 sethi %hi(0xf << 20), %l4 and %l1, %l4, %l4 + andn %l1, %l4, %l1 ba,pt %xcc, __handle_preemption_continue - andn %l1, %l4, %l1 + srl %l4, 20, %l4 /* When returning from a NMI (%pil==15) interrupt we want to * avoid running softirqs, doing IRQ tracing, preempting, etc. |