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| author | Catalin Marinas | 2022-05-20 18:50:57 +0100 |
|---|---|---|
| committer | Catalin Marinas | 2022-05-20 18:50:57 +0100 |
| commit | e003d5335c3877bcbee8d0c347d3c3ee36cdd8b7 (patch) | |
| tree | a73180a13d875674f1bc57ec0484b5d118d3e1ef /arch/x86/entry | |
| parent | 201729d53a34924cfcd011f71e49de9bb2902bd8 (diff) | |
| parent | dffdeade18432d257e0c1845dc4e694f414a9721 (diff) | |
Merge branch 'for-next/sysreg-gen' into for-next/core
* for-next/sysreg-gen: (32 commits)
: Automatic system register definition generation.
arm64/sysreg: Generate definitions for FAR_ELx
arm64/sysreg: Generate definitions for DACR32_EL2
arm64/sysreg: Generate definitions for CSSELR_EL1
arm64/sysreg: Generate definitions for CPACR_ELx
arm64/sysreg: Generate definitions for CONTEXTIDR_ELx
arm64/sysreg: Generate definitions for CLIDR_EL1
arm64/sve: Generate ZCR definitions
arm64/sme: Generate defintions for SVCR
arm64/sme: Generate SMPRI_EL1 definitions
arm64/sme: Automatically generate SMPRIMAP_EL2 definitions
arm64/sme: Automatically generate SMIDR_EL1 defines
arm64/sme: Automatically generate defines for SMCR
arm64/sysreg: Support generation of RAZ fields
arm64/sme: Remove _EL0 from name of SVCR - FIXME sysreg.h
arm64/sme: Standardise bitfield names for SVCR
arm64/sme: Drop SYS_ from SMIDR_EL1 defines
arm64/fp: Rename SVE and SME LEN field name to _WIDTH
arm64/fp: Make SVE and SME length register definition match architecture
arm64/sysreg: fix odd line spacing
arm64/sysreg: improve comment for regs without fields
...
Diffstat (limited to 'arch/x86/entry')
0 files changed, 0 insertions, 0 deletions