diff options
| author | Pu Wen | 2018-09-23 17:34:16 +0800 |
|---|---|---|
| committer | Borislav Petkov | 2018-09-27 18:28:57 +0200 |
| commit | 39dc6f154dac134e4612827cb5283934c1862cb8 (patch) | |
| tree | adb18749a6747690102bf46986b6740e0d083896 /arch/x86/events | |
| parent | d4f7423efdd1419b17524d090ff9ff4024bcf09b (diff) | |
x86/cpu/mtrr: Support TOP_MEM2 and get MTRR number
The Hygon Dhyana CPU has a special MSR way to force WB for memory >4GB,
and support TOP_MEM2. Therefore, it is necessary to add Hygon Dhyana
support in amd_special_default_mtrr().
The number of variable MTRRs for Hygon is 2 as AMD's.
Signed-off-by: Pu Wen <puwen@hygon.cn>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Borislav Petkov <bp@suse.de>
Cc: tglx@linutronix.de
Cc: mingo@redhat.com
Cc: hpa@zytor.com
Cc: x86@kernel.org
Cc: thomas.lendacky@amd.com
Link: https://lkml.kernel.org/r/8246f81648d014601de3812ade40e85d9c50d9b3.1537533369.git.puwen@hygon.cn
Diffstat (limited to 'arch/x86/events')
0 files changed, 0 insertions, 0 deletions