diff options
| author | Len Brown | 2017-01-21 01:15:09 -0500 |
|---|---|---|
| committer | Len Brown | 2017-03-01 00:14:04 -0500 |
| commit | 98af74599ea0757098a5776ea29e581b661dcf6f (patch) | |
| tree | 7ff03bde40b22312ef759a72fbe69185cfbea74d /arch/x86/include/asm | |
| parent | b3a34e9382a4aacfa7c0b24f9548737bbb20338e (diff) | |
x86 msr_index.h: Define MSR_MISC_FEATURE_CONTROL
This non-architectural MSR has disable bits
for various prefetchers on modern processors.
While these bits are generally touched only by the BIOS,
say, via BIOS SETUP, it is useful to dump them
when examining options that can alter performance.
Cc: x86@kernel.org
Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'arch/x86/include/asm')
| -rw-r--r-- | arch/x86/include/asm/msr-index.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 83bc672c225c..312fb7e14cdd 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -467,6 +467,7 @@ #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 +#define MSR_MISC_FEATURE_CONTROL 0x000001a4 #define MSR_MISC_PWR_MGMT 0x000001aa #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 |